U.S. Ser. No. 098,211 discloses late programming an IGFET ROM by ion implantation. By IGFET, we mean an insulated gate field effect transistor. The ROM comprises an orderly array of such transistors. The IGFETs are ordinarily arranged on a common silicon substrate in a pattern such that the gates of individual transistors are aligned in a number of parallel input rows. The drains of individual devices are aligned in a plurality of parallel columns. In a typical array of horizontal type IGFETs, all IGFET drains can be contacted by a metallization pattern of parallel conductor output strips that overlie and, in plan view, are orthogonal to a pattern of parallel polycrystalline silicon gate input strips. The aforementioned U.S. Ser. No. 098,211 discloses programming the ROM by ion implantation through the polycrystalline silicon gate strips just before metallization, using a reflowable glass layer as a mask. In substance, all ROM gates are potentially active when the polycrystalline silicon gate strips are defined. A blanket silicon nitride coating is applied over the polycrystalline silicon gate strips, and contact openings etched in it. A blanket reflowable glass coating is applied over the silicon nitride coatings, and corresponding contact openings etched in it. However, concurrently, ion implant windows are also etched in the glass coating, over selected ROM gates. No additional masks are needed to perform the ion implantation since two masks are ordinarily needed anyway, to etch first through the glass and then through the underlying thermal oxide. The silicon nitride coating provides an insulating coating over the gate strip portion exposed within the ion implant window. Accordingly, metal drain strips can be applied over the glass in the usual manner. They can pass directly over the selected gate ion implant windows without electrically shorting to the gate strip in the window. Thus, not only is the late programming achieved but high ROM layout density is preserved.
On the other hand, the metal drain strips and the gate strip portions overlap within the ion implant windows with only a thin layer of dielectric therebetween. This generates a parasitic capacitance. In small ROM arrays the cumulative effect of this parasitic capacitance is not particularly significant. However, in large ROM arrays it can accumulate sufficiently to significantly slow down ROM operating speed. We have now discovered how to avoid this parasitic capacitance but still obtain late programming, without increasing ROM size. In addition, we have discovered a technique whereby such late programming can be achieved without adding another mask to the ROM manufacturing method, over mask sets typically used in making IGFET ROM arrays.